In an integrated circuit (IC) manufacturing process, various integrated passive devices (IPDs) are implemented in a chip through a front end of line (FEOL). Inductors and transformers are commonly used passive devices in the chip, and are widely applied to various radio frequency (RF) ICs, such as, a low noise amplifier (LNA), a voltage-controlled oscillator (VCO), an injection-locked frequency divider (ILFD), a power amplifier (PA), etc. Although a number of external devices can be reduced by implementing the inductors and transformers in the chip, the passive devices in the chip usually occupy a large chip area, which increases cost of the FEOL.
Packaging technology has been developed from thin small outline packaging (TSOP), chip scale package (CSP), wafer level package (WLP), etc. to stacked package on package (PoP). Design of a semiconductor circuit often encounters a bottleneck, for example, an analog circuit and a digital circuit are not easy to be integrated through a system on chip (SoC) process, or even if the analog circuit and the digital circuit are integrated to the SoC, issues of high cost and being unable to achieve characteristic optimisation are encountered. System in package (SiP) can integrate different devices through a packaging technique. However, when packaging requirements become more complicated, the SiP technique also has a design bottleneck related to operation speed, power consumption, size, etc.
A three-dimension integrated circuit (3DIC) technique can effectively increase product performance, reduce power consumption, cost, volume and integrate heterogeneous ICs. The 3DIC technique can be regarded as another solution of the SoC and SiP techniques. According to the 3DIC technique, chips with different functional properties or even different substrates can be respectively manufactured through most suitable manufacturing processes thereof, and then a through silicon via (TSV) technique is used to implement 3D stacking for integration. The 3DIC technique is not only capable of reducing a length of a metal wire and reducing a wiring resistance, but is also capable of reducing a chip area, and has small volume, high integration, high efficiency, low power consumption and low cost. Before the 3D stacking is performed, fabrication of circuit or system of different chip layers is generally completed through the most suitable FEOL (the IC manufacturing process). After fabrication of the different chip layers is completed, the different chip layers are stacked to each other through TSV, bumps and re-distributed layer (RDL) to implement a stacking step of a back end of line (BEOL) (the packaging process). By implementing various IPDs through the BEOL, not only is a BEOL area effectively used, the IPDs originally implemented in the FEOL is changed to be implemented in the BEOL. By implementing the IPDs through the BEOL, the area of the expensive FEOL is saved to achieve an effect of cost reduction.
Besides consideration of area, there is still a technical issue related to noise. In order reduce a common mode noise, a circuit structure is generally designed to a differential type to increase a differential gain and suppress a common mode noise gain. In this way, the IPDs usually place emphasis on a symmetrical structure to cope with a demand of the differential type. If a transformer adopts the differential type, the symmetrical structure thereof is further emphasized, so as to achieve better differential operation characteristics.